The escalating requirements for high density and performance associated with ultra large scale (ULSI) semiconductor devices require design features of 0.18 .mu.m and below, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 .mu.m and below challenges the limitations of conventional semiconductor manufacturing techniques.
As feature sizes of metal oxide semiconductor (MOS) and CMOS devices plunge into the deep sub-micron range, so called "short channel" effects have arisen which tend to limit device performance. For N-channel MOS transistors, the major limitation encountered is caused by hot-electron-induced instabilities, due to high electrical fields between the source and drain, particularly near the drain, with an attendant injection of charge carriers into the gate or semiconductor substrate. Injection of hot carriers into the gate can cause gate oxide charging and threshold voltage instabilities which accumulate over time and greatly degrade device performance.
For P-channel MOS transistors of short-channel type, the major limitation on performance arises from "punch-through" effects which occur with relatively deep junctions. In such instances, there is a wider sub-surface depletion effect and it is easier for the field lines to go from the drain to the source, resulting in the above-mentioned "punch-through" current problems and device shorting. To minimize this effect, relatively shallow junctions are employed in forming p-channel MOS transistors.
A conventional approach to hot carrier instability problems of MOS and CMOS devices comprises forming lightly- or moderately-doped source/drain extensions just under the gate region, while the moderately or heavily-doped source/drain regions are laterally displaced from the gate by at least one dielectric sidewall spacer on the side surfaces of the gate. Such structures are particularly advantageous because they do not have problems with large lateral or vertical diffusion.
Several processing sequences or schemes have been developed for the manufacture of lightly or moderately-doped source/drain extension-type MOS and CMOS transistors for use in high-density integration applications, with a primary goal of simplifying the manufacturing process by reducing and/or minimizing the requisite number of critical marks and processing steps. See, for example, copending U.S. patent applications Ser. No. 09/277,161 filed on Mar. 26, 1999, and Ser. No. 60/149,420 filed on Aug. 18, 1999, wherein disposable sidewall spacers are employed to significantly reduce the number of masks and process steps in CMOS transistor fabrication. Such disposal sidewall spacer techniques involve reversal of the conventional technique by initially forming moderately or heavily doped source/drain implants, removing the sidewall spacers, and then forming the lightly or moderately doped source/drain extension implants.
There, however, exists a need for a method of manufacturing semiconductor devices with a reduced number of critical masks employing disposable sidewall spacers which can be formed and removed in an efficient, cost effective manner without adversely impacting device integrity. There exists a particular need for such methodology which can be easily implemented into existing processing.